This invention relates generally to digital to analog (D/A) converters and particularly to a digital analog converter which utilizes a conventional n-bit D/A circuit to transform a 2n-bit digital word to analog form.
Generally, the cost, complexity and size of a conventional n-bit digital to analog converter increases rapidly with the number of bits with which the converter is designed to operate. Accordingly, it is desirable that the bit handling capacity of a conventional n-bit D/A converter is increased without substantial increases in cost, complexity size or processing speed. One example of a D/A converter alternately converts selected bits of a multi-bit data word by processing the word through dual D/A converters, each of which accommodate half the number of bits of the word. A time division switching circuit introduces substantial switching transients into the analog processing which further requires a filtering network having a time constant which slows the speed of the conversion process.